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| CY25818/19 Spread Spectrum Clock Generator Features * * * * * * * * 8- to 32-MHz input frequency range CY25818: 8-16 MHz CY25819: 16-32 MHz Separate modulated and unmodulated clocks Accepts clock, crystal, and resonator inputs Down spread modulation Power-down function Low-power dissipation -- CY25818 = 33 mW-typ @ 8 MHz -- CY25818 = 56 mW-typ @ 16 MHz -- CY25819 = 36 mW-typ @ 16 MHz -- CY25819 = 63 mW-typ @ 32 MHz * Low cycle-to-cycle jitter -- SSCLK = 250 ps-typ -- REFOUT = 275 ps-typ * Available in 8-pin (150-mil) SOIC package Applications * * * * * * * * * * Printers and MFPs LCD panels and notebook PCs Digital copiers PDAs Automotive CD-ROM, VCD, and DVD Networking and LAN/WAN Scanners Modems Embedded digital systems Benefits * Peak electromagnetic interference (EMI) reduction by 8-16 dB * Fast time to market * Cost reduction Block Diagram 300K Pin Configuration XIN/CLKIN 1 REFERENCE DIVIDER PD and CP LF XIN/CLKIN 1 VSS 2 8 XOUT XOUT 8 MODULATION CONTROL VDD 7 VCO COUNTER VCO CY25818 CY25819 7 VDD 6 PD# 5 REFCLK S0 3 SSCLK 4 VSS 2 INPUT DECODER 3 6 DIVIDER and MUX 4 5 SSCLK REFCLK 8 Pin SOIC 8-pin SOIC S0 PD# Cypress Semiconductor Corporation Document #: 38-07362 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 28, 2002 CY25818/19 . Pin Description Pin 1 2 3 4 5 6 7 8 Name XIN/CLK VSS S0 SSCLK REFCLK PD# VDD XOUT Power Supply Ground. Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer to Table 2 for the amount of modulation (Spread%). Unmodulated Reference Clock Output. The unmodulated output frequency is the same as the input frequency. Power-Down Control Pin. Default = H (VDD). Positive Power Supply. Clock, Crystal, or Ceramic Resonator Output Pin. Leave this pin unconnected if an external clock is used at XIN pin. The CY25818/19 products are available in an 8-pin SOIC (150-mil) package with a commercial operating temperature range of 0-70C. Contact Cypress for availability of -40 to +85C industrial temperature range operation or TSSOP package versions. Refer to the CY25568, CY25811, CY25812, and CY25814 products for other functions such as clock multiplication of 1x, 2x, or 4x to generate a wide range of Spread Spectrum output clocks from 4 to 128 MHz. Description Clock, Crystal, or Ceramic Resonator Input Pin. Overview The Cypress CY25818/19 products are Spread Spectrum Clock Generator (SSCG) ICs used for the purpose of reducing EMI found in today's high-speed digital electronic systems. The devices use a Cypress proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The input frequency range is 8-16 MHz for the CY25818 and 16-32 MHz for the CY25819. Both products accept external clock, crystal, or ceramic resonator inputs. The CY25818/19 provide separate modulated (SSCLK) and unmodulated reference (REFCLK) clock outputs which are the same frequency as the input clock frequency. Down spread frequency modulation can be selected by the user, based on three discrete values of Spread%. A separate Power-down function is also provided. Table 2. Spread% Selection XIN (MHz) 8-10 10-12 12-14 14-16 16-20 20-24 24-28 28-32 Product CY25818 CY25818 CY25818 CY25818 CY25819 CY25819 CY25819 CY25819 Input Frequency Range and Selection CY25818/19 input frequency range is 8-32 MHz. This range is divided into two segments, as given in Table 1. Table 1. Input and Output Frequency Selection Product CY25818 CY25819 Input/Output Frequency Range 8-16 MHz 16-32 MHz Spread% Selection CY25818/19 SSCG products provide Down-Spread frequency modulation. The amount of Spread% is selected by using 3-Level S0 digital input. Spread% values are given in Table 2. S0 = 1 Down (%) -3.0 -2.7 -2.5 -2.3 -3.0 -2.7 -2.5 -2.3 S0 = 0 Down (%) -2.2 -1.9 -1.8 -1.7 -2.2 -1.9 -1.8 -1.7 S0 = M Down (%) -0.7 -0.6 -0.6 -0.5 -0.7 -0.6 -0.6 -0.5 3-Level Digital Inputs S0 digital input is designed to sense three logic levels designated as HIGH "1," LOW "0," and MIDDLE "M." With this 3-Level digital input logic, the 3-Level logic is able to detect three different logic levels. The S0 pin includes an on-chip 20K (10K/10K) resistor divider. No external application resistors are needed to implement 3-Level logic, as follows. Logic Level "0": 3-Level logic pin connected to GND. Logic Level "M": 3-Level logic pin left floating (no connection.) Logic Level "1": 3-Level logic pin connected to VDD. Document #: 38-07362 Rev. *A Page 2 of 8 CY25818/19 Figure 1 illustrates how to implement 3-Level Logic. L OGI C L OW (0 ) L OGI C MI D D L E (M) L OGI C H I GH (H ) VD D S0 to VS S S0 U N CON N E CT E D S0 to VD D VS S Figure 1. 3-Level Logic Modulation Rate Spread Spectrum Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rates of SSCG clocks are generally referred to in terms of frequency, and fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the Modulation Rate. In the case of CY25818/19 devices, the (Spread Spectrum) Modulation Rate, fmod, is given by the following formula: fmod = fIN/DR where fmod is the Modulation Rate, fIN is the Input Frequency, and DR is the Divider Ratio, as given in Table 3. Table 3. Modulation Rate Divider Ratios Product CY25818 CY25819 Input Frequency Range 8-16 MHz 16-32 MHz Divider Ratio (DR) 256 512 Document #: 38-07362 Rev. *A Page 3 of 8 CY25818/19 Maximum Ratings[1, 2] Supply Voltage (VDD): ..................................................+ 5.5V Input Voltage Relative to VDD: ............................. VDD + 0.3V Input Voltage Relative to VSS: ..............................VSS + 0.3V Operating Temperature:.................................... 0C to +70C Storage Temperature:................................ -65C to + 150C Table 4. DC Electrical Characteristics VDD = 3.3V 10%, TA = 0C to +70C and CL = 15 pF (unless otherwise noted) Parameter VDD VINH VINM VINL VOH1 VOH2 VOL1 VOL2 CIN1 CIN2 IDD1 IDD3 IDD4 Description Power Supply Range Input HIGH Voltage Input MIDDLE Voltage Input LOW Voltage Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input Capacitance Input Capacitance Power Supply Current Power Supply Current Power Supply Current S0 Input S0 Input S0 Input IOH = 4 ma, SSCLK and REFCLK IOH = 6 ma, SSCLK and REFCLK IOL = 4 ma, SSCLK Output IOL = 10 ma, SSCLK Output XIN (Pin 1) and XOUT (Pin 8) All Digital Inputs FIN=8 MHz, no load FIN=32 MHz, no load PD#=VSS 6.0 3.5 7.5 4.5 10.0 19.0 150 Conditions Min. 2.97 0.85 VDD 0.40 VDD 0.0 2.4 2.0 0.4 1.2 9.0 6.0 12.5 23.0 250 Typ. 3.3 VDD 0.50 VDD 0.0 Max. 3.63 VDD 0.60 VDD 0.15 VDD Unit V V V V V V V V pF pF mA mA A Table 5. Timing Electrical Characteristics VDD = 3.3V 10%, TA = 0C to +70C and CL = 15 pF (unless otherwise noted) Parameter ICLKFR1 ICLKFR2 trise1 tfall1 CDCin CDCout CCJss CCJref Description Input Frequency Range Input Frequency Range Clock Rise Time Clock Fall Time Input Clock Duty Cycle Output Clock Duty Cycle Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter CY25818 CY25819 SSCLK and REFCLK, 0.4V to 2.4V SSCLK and REFCLK, 0.4V to 2.4V XIN SSCLK and REFCLK @ 1.5V SSCLK; FIN = FOUT= 8-32 MHz REFCLK; FIN = FOUT = 8-32 MHz Conditions Min. 8 16 2.0 2.0 20 45 3.0 3.0 50 50 250 275 Typ. Max. 16 32 4.0 4.0 80 55 350 375 Unit MHz MHz ns ns % % ps ps Ordering Information Part Number CY25818SC CY25818SCT CY25819SC CY25819SCT 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel Package Type Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Note: 1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Operation at any Absolute Maximum Rating is not implied. Document #: 38-07362 Rev. *A Page 4 of 8 CY25818/19 Characteristics Curves The following curves demonstrate the characteristic behavior of the CY25818/19 when tested over a number of environ300 290 280 270 mental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in Table 4 and Table 5. 20 R E F CL K CY 2 5 8 19 R E F CL K CY 2 5 8 18 19 18 17 C Y 2 58 18 8 - 16 M H z C Y 25 819 16 - 3 2 M H z CCJ (ps) 260 250 240 230 IDD(mA) 16 15 14 13 S S CL K CY2 5 8 19 220 210 S S CL K CY2 5 8 18 12 11 200 8 12 16 20 24 28 32 10 8 12 16 20 24 28 32 F r equ en cy ( MH z ) F r equ en cy ( MH z ) Figure 2. CCJ (ps) vs. Frequency (MHz) 2.75 3.1 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 Figure 4. IDD (mA) vs. Frequency (MHz) 2.5 BW (%) CY25818@8.0 MHz 12 MHz BW % 2.25 32.0 MHz CY25819@32 MHz 2 1.75 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.8 2.9 3 3.1 3.2 VDD (volts) 3.3 3.4 3.5 3.6 3.7 Temp (C) Figure 3. Bandwidth% vs. Temperature Figure 5. Bandwidth% vs. VDD Document #: 38-07362 Rev. *A Page 5 of 8 CY25818/19 SSCG Profiles CY25818/19 SSCG products use a non-linear "optimized" frequency profile as shown in Figure 6 and Figure 7. The use of Cypress proprietary "optimized" frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems. Figure 6. CY25818 Spread Spectrum Profile (Frequency vs. Time)[1] Figure 7. CY25819 Spread Spectrum Profile (Frequency vs. Time)[2] Notes: 1. XIN = 16.0 MHz; S0 = 1; SSCLK = 16.0 MHz; BW = -2.14%. 2. Xin = 32.0MHz; S0 = 1; SSCLK = 32.0 MHz; BW = -2.15% Document #: 38-07362 Rev. *A Page 6 of 8 CY25818/19 Application Schematic VDD C3 0.1 uF 7 C2 1 14.3 MHz or 27.0 MHz XIN VDD 4 27 pF C3 SSCLK XOUT REFCLK 5 8 27 pF 14.3 MHz (CY25818) 27.0 MHz (CY25819) CY25818 CY25819 6 PD# S0 VSS 2 3 Figure 8. Typical Application Schematic Package Drawing and Dimensions 8-lead (150-mil) SOIC S8 51-85066-A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07362 Rev. *A Page 7 of 8 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY25818/19 Document Title: CY25818/19 Spread Spectrum Clock Generator Document Number: 38-07362 REV. ** *A ECN NO. 112462 122701 Issue Date 03/21/02 12/28/02 Orig. of Change OXC RBI New Data Sheet Added power up requirements to maximum rating information. Description of Change Document #: 38-07362 Rev. *A Page 8 of 8 |
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